Latest Posts
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A practical setup memo for running SAM2 video segmentation on Jetson Orin Nano Super with a lightweight, repeatable development workflow. The article covers building a Jetson-compatible PyTorch and transformers container with jetson-containers, mitigating NCCL memory pressure during image builds, cloning and configuring SAM2 with smaller checkpoints for limited-memory environments, and integrating the workflow with VSCode Dev Containers and Jupyter kernels so notebooks can be executed smoothly inside Docker. -
A step-by-step memo for taking a ResNet model through the Vitis AI flow and running inference on AMD Xilinx DPU IP, aimed at people who only revisit the toolchain occasionally. It covers preparing the host-side Vitis AI Docker environment, flashing the official KV260 image with the DPU-enabled platform, understanding where quantization and cross-compilation happen, and using the standard Xilinx tutorial flow to move from a PyTorch model to int8 deployment and runtime inference on FPGA hardware. -
A system-design memo for bringing up MIPI video input and output on Xilinx Zynq platforms using the vendor-provided CSI-2 RX and DSI TX subsystems. The article walks through the role of the D-PHY, AXI Lite, and AXI-Stream interfaces, how to generate and inspect the Vivado example design, how to export the hardware into Vitis, and how to reuse the provided driver examples as a starting point for actual camera and display pipelines built on FPGA video IP. -
A short practical memo on installing and uninstalling Vivado ML on Linux. The article covers the need for a GUI environment, where to obtain the Linux installer, how to grant execution permission and run the installer, the difference between choosing Vitis and Vivado in the installer flow, and how to launch the uninstaller later when cleanup is needed.
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A detailed implementation note on building a custom HDMI graphic display block for Zynq, based on a book workflow but translated into a practical project structure. The post explains the design goals for DDR-backed image display, VGA-class timing, GPIO-controlled addressing, and Vivado IP integration, then breaks down the AXI read control state machine, the display pipeline, and the supporting Verilog modules used to drive video output from programmable logic. -
A practical implementation memo on creating a bit-block display circuit with Vitis HLS and integrating it as an IP block into a Zynq-based design. The article covers the design goals, the circuit specification for alpha blending between two source images, the HLS interface directives applied to the source, synthesis results, C-RTL cosimulation behavior on AXI transactions, and verification of the generated raw output image before exporting the design as RTL IP. -
A hands-on note focused on creating a pattern drawing circuit with Vitis HLS and validating how the synthesized hardware actually behaves. The article follows the flow from project creation and C-based test bench setup through synthesis, C-RTL cosimulation, and waveform inspection in Vivado, using a rectangle fill example to show how image data is generated, how AXI burst transfers appear on the bus, and how to confirm timing and overlap behavior from the resulting traces. -
A practical engineering note on building a custom IP block in Vivado and integrating it into a Zynq-based design. The article covers the Create and Package New IP flow, the basics of AXI bus read and write handling, how slave register writes and reads are decoded in the generated peripheral template, and how to expose additional ports before repackaging the IP and validating the design in a full block design and software environment. -
A practical engineering note on designing a character display circuit in Vivado and packaging it as a custom IP block. The article covers the required display specification, creation of VRAM and CGROM memory blocks using Vivado IP, repackaging of the character display circuit, and simulation-based verification of memory writes and displayed RGB output before moving on to hardware validation. -
A practical engineering note on constructing a hardware system around the Zynq Processing System. The article covers setting up a Zynq PS-based block design in Vivado, adding AXI GPIO for LED and button control, running connection automation, matching ports to constraints, and understanding the warning related to DDR-to-PS clock skew before generating the HDL wrapper for the design. -
A practical engineering note on constructing a MicroBlaze-based hardware platform as an alternative to a Zynq-based design. The article covers the block design setup in Vivado, connection automation, clock and reset configuration, GPIO integration, address map inspection, export to Vitis, and a simple LED control application that verifies software-driven hardware access through the generated register map. -
A practical engineering note on using ChatGPT as a development aid when building a pattern display circuit in HDL. The article covers a basic HDMI pattern generator for VGA output, simulation-based verification using raw image dumps, and a follow-up extension that adds 16-level gradient patterns. It also documents how iterative prompt-and-fix collaboration with ChatGPT was used to diagnose gradient direction issues, blanking-region mistakes, and timing offsets in the generated Verilog.